1. Field of the Invention
This invention relates to data communications processors and to multiprocessor architectures in general and specifically to interrupt and DMA bus request control architecture and methods.
2. Prior Art
Arbitration circuits for arbitrating simultaneously presented contending requests for DMA bus access or processor interrupts have been known previously. An example is the Model 8289 bus arbitor sold by the Intel Company for providing multi-master system bus protocol and synchronization to one of several different kinds of microprocessors. This device is effective in greatly relieving the workload on the processor involved with arbitrating among competing requests at its interface but does little to relieve the overall wiring complexity and cost since an additional expensive element, the arbitor itself, must be added and a plurality of connecting lines must also be utilized between the requesting devices and the arbitor as they were used between the requesting devices and the processor itself. It does not address the problem of arbitrating among competing interrupt requests at the processor.
Similarly, prior art processors have arbitrated requests for bus access or for interrupt service by contending requestors either by periodically polling the requestors in a priority assigning manner or by internally arbitrating competing requests. Either of these approaches requires a significant involvement on the part of the controlling microprocessor which detracts from its capability of processing other tasks and does nothing to alleviate the overall wiring complexity and cost involved in signalling the many competing requests and grants.